Algebra-Logical Diagnosis Model for SoC F-IP

– Algebra-logical model, method and algorithm of fault embedded diagnosis in functional blocks of SoC are proposed. The reduced SoC Functional Intellectual Property Infrastructure that is characterized by minimal set of the embedded diagnosis processes in real time and enables to realize the services: testing of the nominal functions on basis of generable input patterns and analysis of output reactions; fault diagnosis with given resolution of fault location by means of utilization of the IEEE 1500 multiprobe; fault simulation to provide of realization of the first two procedures on basis of the fault detection table is presented. Key-Words: Diagnosis, System-on-Chip, Electronic System Level, Transaction Level Modelling, Infrastructure Intellectual Property, Functional Intellectual Property, Testbench, Fault 1 I-IP Infrastructure Computational and hardware complexity of modern digital systems on a chip (SoC) is characterized by millions of equivalent gates and requires making and implementation of new high-level design technologies: Electronic System Level (ESL) Design, Transaction Level Modelling (TLM) and embedded service – Infrastructure Intellectual Property (I-IP). It means that search for high-performance methods and facilities [1-12, 15-17] reduces all researchers to necessity to rise of an abstraction level of Functional Intellectual Property (F-IP) models, which are created and embedded into a chip. EDA market suggests facilities for computer-aided modelling and verification of system level devices, beginning with HDLcompilers (C++, SystemC, SystemVerilog, UML, SDL) [7] up to graphics environments (Simulink, LabView, Xilinx EDK). These facilities enable to create projects using existing library components by means of ESL-mapping and creation of TLMinterfaces [8, 9]. Market appeal of the implementation of a digital system to FPGA is determined by the followings: application of relatively cheap chips instead of the universal processors, low power consumption, small overall size, qualitative and reliable realization of the main functions due to on-chip IIP-infrastructure that is urgent in the century of mobile computers. The research aim is development of algebra-logical method of SoC Functional Intellectual Property Infrastructure that is intended for the diagnosis of SoC components in real time. The problems: 1) State of the market of SoC Infrastructure Intellectual Property technologies; 2) Algebra-logical (AL) method of Infrastructure Intellectual Property on basis of the cover matrix; 3) Application of the AL-method to diagnosis of SoC components; 4) Practical results. Modern design technologies of digital systems on chips propose along with creation of functional blocks F-IP development of service modules I-IP, which are oriented on complex solving of the project quality problem and yield increasing in manufacturing that is determined by implementation of the following services into a chip [8]: 1) Observation for state of input and output lines in functioning, verification and testing of standard blocks on basis of utilization of the boundary scan standard IEEE 1500 [10, 12]; 2) Testing of functional modules by means of input of the fault detection patterns from different test generators, which are oriented on verification of faults or fault-free state; 3) Fault diagnosis by means of analysis of an information obtained on the testing stage and utilization of special methods of embedded fault lookup on basis of the standard IEEE 1500 [10,12]; 4) Repair of functional modules and memory after fixation of negative testing result, fault location and its type on diagnosis stage; 5) Measurement of the general characteristics and parameters of a device operation on basis of on-chip facilities, which enable to make time and voltampere measurements; WSEAS TRANSACTIONS on CIRCUITS AND SYSTEMS Vladimir Hahanov, Vladimir Obrizan, Eugenia Litvinova, Ka Lok Man